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RT8026 1 ds8026-02 march 2011 www.richtek.com features z z z z z input voltage range : 2.7v to 5.5v z z z z z adjustable output voltage : 1v to v in z z z z z output current : 1a z z z z z high efficiency : up to 95% z z z z z no schottky diode required z z z z z 1.5mhz fixed frequency pwm operation z z z z z current limiting protection z z z z z thermal shutdown protection z z z z z small msop-10 package z z z z z rohs compliant and halogen free applications z mobile phones z personal information appliances z wireless and dsl modems z mp3 players z portable instruments 1.5mhz, 1a, high efficiency pwm step-down dc/dc converter general description the RT8026 is a high-efficiency pulse-width-modulated (pwm) step-down dc/dc converter. capable of delivering 1a output current over a wide input voltage range from 2.7v to 5.5v, the RT8026 is ideally suited for portable electronic devices that are powered from 1-cell li-ion battery or from other power sources such as cellular phones, pdas and hand-held devices. two operating modes are available including : pwm/low- dropout autoswitch and shut-down modes. the internal synchronous rectifier with low r ds(on) dramatically reduces conduction loss at pwm mode. no external schottky diode is required in practical application. the RT8026 enters low-dropout mode when normal pwm cannot provide regulated output voltage by continuously turning on the upper p-mosfet. the RT8026 enter shut- down mode and consumes less than 0.1 a when the en pin is pulled low. the switching ripple is easily smoothed-out by small package filtering elements due to a fixed operating frequency of 1.5mhz. this along with small msop-10 package provides small pcb area application. other features include soft start, lower internal reference voltage with 2% accuracy, over temperature protection, and over current protection. ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. marking information for marking information, contact our sales representative directly or through a richtek distributor located in your area. pin configurations (top view) msop-10 pgnd nc vin nc gnd lx en fb nc nc 5 6 7 8 4 3 2 10 9 RT8026 package type f : msop-10 lead plating system g : green (halogen free and pb free)
RT8026 2 ds8026-02 march 2011 www.richtek.com function block diagram functional pin description pin no. pin name pin function 1 vin power input. 2, 4, 6, 7 n c no internal connection. 3 gnd ground pin. 5 fb feedback input pin. receives the feedback voltage from a resistive divider connected across the output. 8 en chip enable (active high). it is recommended to add a 100k ? resistor between en and gnd pin. 9 lx pin for switching. connect this pin to the inductor. 10 pgnd power ground pin. typical application circuit figure 1. typical application circuit for RT8026 ? ? ? ? ? ? + = r2 r1 1 x v v ref out with r2 = 300k to 60k so the i r2 = 2 a to 10 a, and (r1 x c1) should be in the range between 3x10 -6 and 6x10 -6 for component selection. 4.7f 10f vin lx RT8026 en fb 2.2h 2.7v to 5.5v v in v out c in l 5 9 1 8 c out r1 r2 c1 i r2 3 gnd pgnd 10 comp rc rs1 rs2 en vin lx fb uvlo & power good detector v ref slope compensation current sense osc & shutdown control current limit detector driver control logic pwm comparator error amplifier gnd current detector pgnd
RT8026 3 ds8026-02 march 2011 www.richtek.com absolute maximum ratings (note 1) z supply input v oltage ------------------------------------------------------------------------------------------------------ 6.5v z en, fb pin voltage ------------------------------------------------------------------------------------------------------- ? 0.3v to v in z power dissipation, p d @ t a = 25 c msop-10 -------------------------------------------------------------------------------------------------------------------- 833mw z package thermal resistance (note 2) msop-10, ja -------------------------------------------------------------------------------------------------------------- 120 c/w z lead temperature (soldering, 10 sec.) ------------------------------------------------------------------------------- 260 c z storage temperature range -------------------------------------------------------------------------------------------- ? 65 c to 150 c z junction temperature ----------------------------------------------------------------------------------------------------- 150 c z esd susceptibility (note 3) hbm (human body mode) ---------------------------------------------------------------------------------------------- 2kv mm (ma chine mode) ------------------------------------------------------------------------------------------------------ 200v electrical characteristics (v in = 3.6v, v out = 2.5v, v ref = 0.6v, l = 2.2 h, c in = 4.7 f, c out = 10 f, t a = 25 c unless otherwise specified) parameter symbol test conditions min typ max unit quiescent current i q i out = 0ma, v fb = v ref + 5% -- 50 70 a shutdown current i sh dn en = gnd -- 0.1 1 a r eferenc e v ol tage v ref for adjustable output voltage 0.588 0.6 0.612 v adjustable output range v out (note 6) 1 -- v in ? 0.2v v output voltage accuracy v out v in = v out + v to 5.5v 0a < i out < 1a (note 5) ? 3 -- +3 % fb input current i fb v fb = v in ? 50 -- 50 na pmosfet r on r ds(on)_p i out = 200ma, v in = 3.6v -- 0.28 -- n mosfet r on r ds(on)_n i out = 200ma, v in = 3.6v -- 0.25 -- p-channel current limit i lim_p v in = 2.7v to 5.5 v 1.2 1.5 -- a en high-level input voltage v en_h v in = 2.7v to 5.5v 1.5 -- -- v en low-level input voltage v en_l v in = 2.7v to 5.5v -- -- 0.4 v under voltage lock out threshold uvlo -- 1.8 -- v uvlo hysteresis -- 0.1 -- v oscillator frequency f osc v in = 3.6v, i out = 100ma 1.2 1.5 1.8 mhz thermal shutdown temperature tsd -- 160 -- c max. duty cycle 100 -- -- % recommended operating conditions (note 4) z supply input voltage, v in ------------------------------------------------------------------------------------------------ 2.7v to 5.5v z junction temperature range -------------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range -------------------------------------------------------------------------------------------- ? 40 c to 85 c
RT8026 4 ds8026-02 march 2011 www.richtek.com note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a high effective four layers thermal conductivity test board of jedec 51-7 thermal measurement standard. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. note 5. v = i out x p rds(on) note 6. guarantee by design.
RT8026 5 ds8026-02 march 2011 www.richtek.com typical operating characteristics output voltage vs. temperature 3.40 3.43 3.45 3.48 3.50 3.53 3.55 3.58 3.60 -50 -25 0 25 50 75 100 125 temperature (c) output voltage (v) v in = 5v, i out = 0ma frequency vs. input voltage 1.30 1.33 1.35 1.38 1.40 1.43 1.45 1.48 1.50 4 4.25 4.5 4.75 5 5.25 5.5 input voltage (v) frequency (mhz ) v out = 3.5v, i out = 300ma frequency vs. temperature 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 -50-250 255075100125 temperature (c) frequency (mhz ) v in = 5v, v out = 3.5v, i out = 300ma current limit vs. input voltage 1.40 1.45 1.50 1.55 1.60 1.65 1.70 4 4.25 4.5 4.75 5 5.25 5.5 input voltage (v) current limit (a) v out = 3.5v current limit vs. temperature 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 -50-250 255075100125 temperature (c) current limit (a) v in = 5v, v out = 3.5v efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 output current (a) efficiency (%) v out = 3.5v v in = 5.5v v in = 5v
RT8026 6 ds8026-02 march 2011 www.richtek.com en threshold vs. temperature 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 -50 -25 0 25 50 75 100 125 temperature (c) en voltage (v) rising falling v out = 3.5v en threshold vs. input voltage 0.50 0.60 0.70 0.80 0.90 1.00 1.10 1.20 4 4.3 4.6 4.9 5.2 5.5 input voltage (v) en voltage (v) v out = 3.5v rising falling output voltage vs. output current 3.535 3.540 3.545 3.550 3.555 3.560 0 0.2 0.4 0.6 0.8 1 output current (a) ouptut voltage (v) v in = 5.5v v in = 5v power on from en time (100 s/div) v en (5v/div) v out (2v/div) i in (1a/div) v in = 5v, v out = 3.5v, i out = 10ma uvlo threshold vs. temperature 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 -50 -25 0 25 50 75 100 125 temperature (c) input voltage (v) v out = 3.5v rising falling output ripple time (500ns/div) v out (10mv/div) v lx (5v/div) v in = 5v, v out = 3.5v, i out = 500ma
RT8026 7 ds8026-02 march 2011 www.richtek.com load transient response time (50 s/div) i out (500ma/div) v out (50mv/div) v in = 5v, v out = 3.5v, i out = 50ma to 500ma load transient response time (50 s/div) i out (500ma/div) v out (50mv/div) v in = 5v, v out = 3.5v, i out = 50ma to 1a power off from en time (100 s/div) v en (5v/div) v out (2v/div) i in (1a/div) v in = 5v, v out = 3.5v, i out = 1a power on from en time (100 s/div) v en (5v/div) v out (2v/div) i in (1a/div) v in = 5v, v out = 3.5v, i out = 1a
RT8026 8 ds8026-02 march 2011 www.richtek.com ? ? ? ? ? ? + out l out 8fc 1 esr i v applications information the basic RT8026 application circuit is shown in the typical application circuit. external component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by c in and c out . inductor selection for a given input and output voltage, the inductor value and operating frequency determine the ripple current. the ripple current i l increases with higher v in and decreases with higher inductance. having a lower ripple current reduces the esr losses in the output capacitors and the output voltage ripple. highest efficiency operation is achieved at low frequency with small ripple current. this, however, requires a large inductor. a reasonable starting point for selecting the ripple current is i l = 0.4(i max ). the largest ripple current occurs at the highest v in . to guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation : inductor core selection once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or mollypermalloy cores. actual core loss is independent of core size for a fixed inductor value but it is very dependent on the inductance selected. as the inductance increases, core losses decrease. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. ferrite core material saturates ? hard ? , which means that inductance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in ? ? ? ? ? ? ? ? ? ? ? ? ? = in out out l v v 1 l f v i ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = in(max) out l(max) out v v 1 i f v l inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! different core materials and shapes will change the size/ current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and don ? t radiate energy but generally cost more than powdered iron core inductors with similar characteristics. the choice of which style inductor to use mainly depends on the price vs. size requirements and any radiated field/emi requirements. c in and c out selection the input capacitance, c in , is needed to filter the trapezoidal current at the source of the top mosfet. to prevent large ripple voltage, a low esr input capacitor sized for the maximum rms current should be used. rms current is given by : 1 v v v v i i out in in out out(max) rms ? = this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. the selection of c out is determined by the effective series resistance (esr) that is required to minimize voltage ripple and load step transients, as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response as described in a later section. the output ripple, v out , is determined by : the output ripple is highest at maximum input voltage since i l increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance
RT8026 9 ds8026-02 march 2011 www.richtek.com output voltage programming the resistive divider allows the v fb pin to sense a fraction of the output voltage as shown in figure 2. ) r2 r1 (1 v v ref out + = where v ref is the feedback reference voltage (0.6v typ.). for adjustable output voltage mode, the output voltage is set by an external resistive divider according to the following equation : density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to significant ringing. using ceramic input and output capacitors higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. figure 2. setting the output voltage RT8026 gnd fb r1 r2 v out efficiency considerations the efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. efficiency can be expressed as : efficiency = 100% ? (l1+ l2+ l3+ ...) where l1, l2, etc. are the individual losses as a percentage of input power. although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses : vin quiescent current and i 2 r losses. the vin quiescent current loss dominates the efficiency loss at very low load currents whereas the i 2 r loss dominates the efficiency loss at medium to high load currents. in a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence. 1. the vin quiescent current is due to two components : the dc bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. the gate charge current results from switching the gate capacitance of the internal power mosfet switches. each time the gate is switched from high to low to high again, a packet of charge q moves from v in to ground. the resulting q/ t is the current out of v in that is typically larger than the dc bias current. in continuous mode, i gatechg = f(q t +q b ) where q t and q b are the gate charges of the internal top and bottom switches. both the dc bias and gate charge checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to i load (esr), where esr is the effective series resistance of c out . i load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem.
RT8026 10 ds8026-02 march 2011 www.richtek.com losses are proportional to v in and thus their effects will be more pronounced at higher supply voltages. 2. i 2 r losses are calculated from the resistances of the internal switches, r sw and external inductor r l . in continuous mode the average output current flowing through inductor l is ? chopped ? between the main switch and the synchronous switch. thus, the series resistance looking into the lx pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows : r sw = r ds(on)top x dc + r ds(on)bot x (1 ? dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. thus, to obtain i 2 r losses, simply add r sw to r l and multiply the result by the square of the average output current. other losses including c in and c out esr dissipative losses and inductor core losses generally account for less than 2% of the total loss. layout considerations for the best performance of the RT8026, the following guidelines must be strictly followed . ` the input capacitor should be placed as close as possible to the device pins (vin and gnd). ` the lx node is with high frequency voltage swing. it should be kept at a small area. ` place the feedback components as close as possible to the ic and keep away from the noisy devices. ` the gnd and pgnd should be connected to a strong ground plane for heat sinking and noise protection. thermal considerations for continuous operation, do not exceed absolute maximum operation junction temperature. the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = ( t j(max) ? t a ) / ja where t j(max) is the maximum operation junction temperature 125 c, t a is the ambient temperature and the ja is the junction to ambient thermal resistance. for recommended operating conditions specification of RT8026, the maximum junction temperature is 125 c.the junction to ambient thermal resistance ja is layout dependent. for msop-10 packages, the thermal resistance ja is 120 c/w on the standard jedec 51-7 four layers thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula : p d(max) = (125 c ? 25 c) / (120 c/w) = 0.833w for msop-10 packages the maximum power dissipation depends on operating ambient temperature for fixed t j(max) and thermal resistance ja . for RT8026 packages, the figure 3 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. figure 3. derating curves for RT8026 packages 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 153045607590105120135 ambient temperature (c) maximum power dissipation (w ) four layers pcb
RT8026 11 ds8026-02 march 2011 www.richtek.com layout note: 1. the distance that c in connects to v in is as close as possible (under 2mm). 2. c out should be placed near the RT8026. l1 c in c out v in r1 c f c in must be placed as close as possible to the ic lx should be connected to inductor by wide and short trace, keep sensitive compontents away from this trace output capacitor must be placed near the RT8026 place the feedback componen ts as close as possible to the fb pin. RT8026 fb nc nc lx en nc gnd pgnd vin nc 10 2 3 9 8 7 5 4 6 r2 component supplier l1 ( h) c out ( f) r1 (k ) r2 (k ) v out (v) taiyo yuden 10 10 300 62 3.5 taiyo yuden 10 10 120 27 3.3 gotrend 2.2 10 200 62 2.5 gotrend 2.2 10 150 75 1.8 gotrend 2.2 10 100 100 1.2 table 1. recommended components for different output voltage application figure 4. layout guide
RT8026 12 ds8026-02 march 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension l a2 a b a1 d e1 e e dimensions in millimeters dimensions in inches symbol min max min max a 0.810 1.100 0.032 0.043 a1 0.000 0.150 0.000 0.006 a2 0.750 0.950 0.030 0.037 b 0.170 0.270 0.007 0.011 d 2.900 3.100 0.114 0.122 e 0.500 0.020 e 4.800 5.000 0.189 0.197 e1 2.900 3.100 0.114 0.122 l 0.400 0.800 0.016 0.031 10-lead msop plastic package

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